Dear All,

VEDA IIT has now announced Written Test for the selection of bright engineers at National level to the posts of Engineer Trainees in VLSI Logic Design and Physical Design. Written Test will be conducted for eligible candidates on 13th December, 2009 at 10.00 AM at the Designated Centres. Candidates successful in the Witten Test will be called for Interviews and final selected candidates will be provided sponsored training in the respective areas.

Final year students who need to do the project work in the final semester can also apply.

Interested candidates can apply on or before December 10, 2009 at http://www.vedaiit. com/careers. htm.

Please visit www.vedaiit. com for more information and further details.

Note: Candidates who appeared for VEDA IIT Test in the last 6 months are not eligible to apply.

Career opportunities also exist for the competent and experienced engineers working in ASIC Design & Verification and aspiring to move to physical design. Based on the experience level, they may be asked to appear for the written test or attend the interview directly. Apart from submitting web application, such experienced candidates will need to send their resume to careers@vedaiit. com indicating their online registration number in the subject line.

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